In general, the probability that a manufacturing flaw or “fault” will occur within an IC increases as the size of the die used to implement that IC increases. The occurrence of a manufacturing fault within an IC can result in a reduction, or a complete failure, in the operability of the IC. For this reason, it can be more cost effective to divide the circuits to be implemented within the IC across multiple dies. With a multi-die approach, a manufacturing fault occurring on any one of the dies renders only that individual die inoperable and not the entire IC. By implementing the IC using multiple dies as opposed to a single larger die, less die area of the IC becomes unusable when a manufacturing fault renders one of the dies inoperable.
Using a multi-die approach, ICs can be implemented with multiple dies placed within a single package. Implementing an IC with multiple dies requires a partitioning of circuits of the IC among two or more dies. Partitioning circuits of the IC among multiple dies results in the creation of one or more inter-die signals. In order to pass these inter-die signals between dies, each die can be mounted upon a silicon interposer that includes conductive interconnect material that can electrically couple the two or more dies. The interposer can be mounted within a single IC package. In order to couple each die to the IC package, through silicon vias (TSVs) can be implemented within the silicon interposer. Each TSV creates a vertical conductive path from a coupling point on a die, through the interposer, to a coupling point within the IC package or a node external to the package. Through a TSV, the die can be coupled to a signal or power supply external to the IC package.